Morteza Baradaran

Morteza Baradaran

Graduate Research Assistant

Morteza Baradaran

About Me

I’m a Ph.D. student in Computer Science Department at the University of Virginia, advised by Prof. Kevin Skadron. My work spans computer architecture and domain-specific accelerators, with a focus on Processing-in-Memory (PIM) and efficient systems for graph analytics, video/vision models, and genomics.

I enjoy building end-to-end systems—prototyping hardware-aware kernels, writing scalable C/C++/Python code, and validating ideas on real platforms. Download my CV (PDF)

Research Interests

  • Processing-in-Memory (PIM) architectures & memory-centric acceleration
  • Domain-specific accelerators for LLM inference and video segmentation
  • High-performance genomics (fast partial matching and alignment)
  • Compiler/hardware co-design and performance modeling

Education

  • Ph.D., Computer Science — University of Virginia (Sep 2021 – present)
    GPA: 3.95 | Advisor: Prof. Kevin Skadron
  • M.Sc., Computer Architecture — Sharif University of Technology (Sep 2010 – Jun 2012)
    Advisor: Prof. H. Sarbazi-Azad
  • B.Sc., Computer Engineering — Shahed University (Sep 2006 – Jun 2010)

Selected Research Projects

Accelerating Computer Vision Tasks using Processing-in-Memory

Designed a PIM-enabled architecture to accelerate hybrid Transformer–CNN models (e.g., SAM2) by addressing memory bottlenecks in the memory encoder and cross-attention layers, improving both throughput and memory efficiency.

TriPIM: Triangle Counting on UPMEM PIM

Exact triangle counting mapped to DPUs using a binary-search-based algorithm.
GitHub

Sangam: A Chiplet-Based DRAM-PIM Accelerator with CXL Integration for LLM Inferencing

Scalable accelerator for LLM inference combining chiplet PIM and CXL integration.

PIMeval & PIMbench

Open frameworks for PIM simulation and benchmarking.
GitHub | Paper

PARMIK: PArtial Read Matching with Inexpensive K-mers

Fast and memory-efficient metagenomic aligner surpassing BLAST in speed and accuracy.
GitHub | Preprint

Swift: Multi-FPGA Graph Analytics Framework

A scalable framework that distributes graph workloads across multiple FPGAs, overcoming memory capacity bottlenecks and improving throughput for large-scale graph analytics.
Paper

ECG: Expressive Caching for Graphs

Encoding graph locality to improve cache prefetching and replacement policies.
GitHub | Paper

Energy Consumption Analysis of Instruction Cache Prefetching

Evaluated the energy impact of instruction cache prefetching policies using ChampSim for simulation and CACTI-7 for energy modeling, identifying trade-offs between performance gains and power overhead.
GitHub | Paper

Publications (Selected)

  • TriPIM — International Symposium on Memory Systems (MEMSYS), 2025
  • Swift — International Conference on Field-Programmable Technology (FPT), 2024
  • Architectural Modeling and Benchmarking for Digital DRAM PIM — IISWC 2024
  • ECG: Expressing Locality and Prefetching for Optimal Caching in Graph Structures — IPDPSW 2024
  • HashMem: PIM-based Hashmap Accelerator — ISCA 2023 Workshop

Presentations

  • TECHCON 2024 (Oral) — TriPIM: Efficient Triangle Counting on PIM Technologies
  • Genome Informatics 2023 (Poster) — Partial Matching Approach for Pathogen Surveillance

Professional Service

  • Reviewer — Journal of Supercomputing (JS), 2024–present
  • Co-reviewer — International Conference on Computer Design (ICCD), 2023

Teaching

  • CS3130 – Computer Systems & Organization 2 (Fall 2024) — Teaching Assistant
  • CS4414 – Operating Systems (Fall 2022, 2023) — Teaching Assistant

Skills

  • Languages: C/C++, CUDA, Python, Java, Verilog, Bash, Assembly
  • Tools: Gem5, SniperSim, DRAMsim3, ChampSim, CACTI, UPMEM Functional Sim
  • Benchmarks: GAP, Gunrock, Ligra, prim-benchmarks, InSituBench, SPEC/PARSEC

Contact

📍 Rice Hall, University of Virginia
✉️ rgq5aw@virginia.edu
🔗 GitHub | LinkedIn